1. Why it matters: the gap between RISC-V's momentum and the availability of certified, open-source real-time software for high-assurance domains such as automotive, industrial, medical, and aerospace.

2. Making the port future-proof: how to restructure a mature RTOS port so one codebase serves both 32-bit and 64-bit RISC-V, and how to handle modular ISA extensions without fragmenting the build.

3. Lessons from the trenches: the pitfalls of porting battle-tested embedded code to RISC-V, and what we'd do differently.

4. From simulation to real silicon: moving from QEMU to a reference board support package on actual hardware (SpacemiT K1 hardware).

5. Keeping it reliable: automated hardware-in-the-loop testing on physical boards as a guard against regressions.

6. What's next: where ThreadX on RISC-V is heading and how the community can use it and contribute.

OCX Webinar Week - Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V